Synthesizing Portfolio...

Hi, my name is

Edidi Sai Anant.

I architect the future of hardware.

As a specialist in VLSI design and computer architecture, I transform complex computational challenges into efficient, high-performance silicon. Master's graduate from NUS with expertise in semiconductor processes, IC design, and embedded systems.

About Me

I am a recent Master of Science graduate in Electrical Engineering from the National University of Singapore (NUS), specializing in Nanoelectronics, Embedded Systems, and Digital Design. My academic journey has provided me with a robust foundation in both the theoretical and practical aspects of VLSI and semiconductor technology.

Driven by a passion for innovation, I am now seeking opportunities to apply my skills to challenging projects in the semiconductor industry, contributing to the development of next-generation technology. My expertise spans from RTL design and verification to system-level architecture and optimization.

Strengths: Reliable, Patient, and a Collaborative Team Player

Education

Master of Science, Electrical Engineering

National University of Singapore

2023 - 2025

Relevant Courses:

  • VLSI Digital Circuit Design
  • Memory Technologies and Their Emerging Applications
  • Embedded Hardware System Design

Bachelor of Technology, ECE

SRM Institute of Science and Technology

2019 - 2023

Relevant Courses:

  • Digital Electronics Principles
  • Semiconductor Device Modelling
  • Analog Electronic Circuits
  • VLSI Design
  • ARM-Based Embedded System Design

Professional Experience

Graduate Assistant @ National University of Singapore

Aug 2024 - Nov 2024 • 4 mos

Singapore • On-site

  • Oversaw laboratory sessions and assisted with assignments and grading for EE2028 Microcontroller Programming and Interfacing and CG3207 Computer Architecture
  • Provided guidance and feedback on lab work to enhance student understanding
  • Collaborated with faculty to overhaul lab materials and processes, improving educational outcomes
  • Demonstrated strong interpersonal communication and collaborative skills in academic environment

Project Intern @ Maven Silicon

Dec 2022 - Jan 2023 • 2 mos

Bangalore, India • Remote

  • Developed expertise in analyzing project requirements to establish clear and efficient development plans
  • Designed an AHB to APB bridge, tailoring it to meet specific project needs and facilitating seamless communication between distinct bus protocols
  • Decomposed complex designs into modular components, increasing manageability and design efficiency
  • Executed module-level design, honing the ability to realize projects from concept to completion with keen attention to detail
  • Advanced proficiency in writing robust, functional RTL code in Verilog HDL, ensuring optimal performance
  • Interpreted RTL descriptions into gate-level schematics and refined design for efficiency and reliability
  • Synthesized individual modules into a unified, top-tier system architecture, ensuring cohesive operation and performance

Intern @ Sandeepani School of Embedded System Design

Jun 2022 - Jul 2022 • 2 mos

Bangalore, India • Remote

  • Collaborated on the development and meticulous verification of a UART protocol using Verilog HDL, concentrating on data transmission reliability and system integrity
  • Executed in-depth functional verification of a Half Adder utilizing SystemVerilog, ensuring alignment with precise performance specifications
  • Performed detailed functional coverage analysis employing QuestaSim, aiming for exhaustive assessment and optimization of test scenarios
  • Understanding of the basics of System Verilog and workflow for verification of a DUT
  • Generated Random Stimuli for testing larger test case scenarios and developed coverage for DUT
  • Gained expertise in Object Oriented Concepts with System Verilog

Featured Projects

VLSI Interconnect Modelling

Cadence Spice 45nm

Optimized processor interconnects using Elmore RC models and Cadence Virtuoso for a 2-core processor at 45nm technology, focusing on energy-delay tradeoffs.

Standard Cell IP Development

Cadence 40nm DRC/LVS

Created a ring oscillator Standard Cell IP leveraging hierarchical design in Cadence Virtuoso, targeting efficiency in 40nm technology with focus on minimizing area.

FPGA Hardware Accelerator

FPGA HLS Verilog

Developed a hardware accelerator on Xilinx Zynq-7000 FPGA to improve MLP neural network inference with pipelining and loop unrolling optimizations.

In-Memory Compute Circuit

NeuroSim PyTorch Neural Networks

Designed an in-memory compute circuit using NeuroSim and MuMax3 to accelerate neural network computations with quantization techniques.

AHB-APB Bridge Design

Verilog RTL AMBA

Developed a synthesizable AHB to APB bridge with reversible logic-based error detection and correction module for enhanced data integrity.

Autonomous Vehicle Control

Embedded IoT Safety Systems

Developed an intelligent system for autonomous vehicles that detects driver medical distress and responds automatically to ensure safety.

Publications & Patents

Publications

Improving Data Integrity with Reversible Logic-based Error Detection and Correction Module on AHB-APB Bridge

IEEE • Jun 1, 2023

Research on enhancing data integrity in bus bridge architectures using reversible logic techniques.

A Survey on Affordable Internet of Things(IoT) Enabled Healthcare Systems

Grenze Scientific Society • Jul 25, 2022

Comprehensive survey on cost-effective IoT solutions for healthcare applications.

Patents

A SYSTEM FOR CONTROLLING AN AUTONOMOUS VEHICLE AND A METHOD THEREOF

Patent No: 202341043496 • Issued Mar 28, 2025

This project focuses on developing an intelligent system for autonomous vehicles that can detect when a driver is experiencing medical distress and respond automatically to ensure safety. The system continuously monitors the driver's vital signs and behavior patterns.

Certifications

Google

Foundations of Project Management

Nov 2024

Credential ID: KM46R8IMF5CV

Internshala

Arduino

Jan 2022

Credential ID: 4T534G1-F091-22AD-D21D-C3A3719DE516

edX

Building a RISC-V CPU Core

Nov 2021

Credential ID: 69e64197e97c496cbe01af6778a79485

Coursera

Python for Data Science, AI & Development

Sep 2021

Credential ID: RAGLUQQCSWSH

Internshala

PCB Design

Nov 2021

Credential ID: B648F348-EE2C-61F7-5EE0-024958B856E1

Cisco

Introduction to IoT and Digital Transformation

Oct 2021

Credential ID: NJL2VNV9CYXQ

Technical Skills

Programming Languages

C++
Python
Verilog
SystemVerilog
HLS

EDA Tools

Cadence Virtuoso
Xilinx Vivado
QuestaSim
Xilinx Vitis

Embedded Systems

Arduino
Raspberry Pi
NodeMCU

Design & Documentation

Autodesk Eagle
LaTeX

What's Next?

Get In Touch

I'm actively seeking innovative roles where I can apply my skills to solve complex challenges in the semiconductor industry. If you're building something remarkable in VLSI, computer architecture, or embedded systems, I'd love to connect and discuss how we can create the future of hardware together.