NAND EFA · Micron NTI · Singapore
Edidi Sai Anant.
Electrical Failure Analysis on NAND flash at Micron's R&D group in Singapore. I trace fail signatures and isolate root causes across the full FA workflow.
01About
Currently at Micron Technology in Singapore, doing Electrical Failure Analysis on NAND memory devices within the NTI (NAND Technology Integration) R&D group. I investigate electrical fail signatures from triage through physical localization to root-cause determination.
Before that: an MSc in Electrical Engineering from NUS, specializing in Nanoelectronics, with coursework in memory technologies, VLSI design, and embedded hardware systems. I also served as a Graduate Assistant for microcontroller programming and computer architecture labs.
I find the intersection of hardware and software genuinely interesting, and I am comfortable working across both.
Outside of work: I enjoy solving puzzles, cooking, gaming, music, and travelling.
At a glance
02Work
NAND EFA Engineer @ Micron Technology
- Perform electrical failure analysis on NAND memory devices within the NTI (NAND Technology Integration) R&D group
- Investigate fail signatures to determine root cause, from electrical verification through physical localization and mechanism understanding
- Support yield and debug teams by translating electrical failure data into actionable engineering conclusions
- Work at the intersection of hardware characterization, circuit analysis, and software tooling
Graduate Assistant @ National University of Singapore
- TA for EE2028 (Microcontroller Programming and Interfacing) and CG3207 (Computer Architecture)
- Ran lab sessions, graded assignments, gave feedback on lab work
- Collaborated with faculty to overhaul lab materials to improve clarity and reduce common student errors
- Developed strong technical communication skills through lab instruction and student mentoring
Project Intern @ Maven Silicon
- Designed a synthesizable AHB to APB bus bridge in Verilog HDL, including a reversible logic-based error detection and correction module
- Decomposed complex design into modular components from RTL through gate-level synthesis
- This work resulted in an IEEE publication on data integrity in bus bridge architectures
Intern @ Sandeepani School of Embedded System Design
- Developed and verified a UART protocol implementation in Verilog HDL
- Ran functional verification of a Half Adder in SystemVerilog with QuestaSim coverage analysis
- Gained foundational exposure to verification methodology including random stimuli and coverage-driven testing
03Projects
VLSI Interconnect Modelling
Optimized processor interconnects using Elmore RC models and Cadence Virtuoso for a 2-core processor at 45nm. Focused on energy-delay tradeoffs and signal integrity.
Standard Cell IP Development
Ring oscillator Standard Cell IP in Cadence Virtuoso at 40nm. Hierarchical design, DRC/LVS clean, area-minimized with PVT corner analysis.
FPGA Hardware Accelerator
MLP neural network inference accelerator on Xilinx Zynq-7000. Implemented in software, HLS, and Verilog. Profiled and optimized with pipelining, loop unrolling, and array partitioning.
In-Memory Compute Circuit
In-memory compute circuit using NeuroSim for neural network acceleration. Explored quantization float64 → int4 and its effect on accuracy vs. efficiency tradeoffs.
AHB-APB Bridge + ECC
Synthesizable AHB to APB bridge with reversible logic-based error detection and correction. Led to an IEEE publication on data integrity in bus bridge architectures.
Autonomous Vehicle Safety System
Intelligent system detecting driver medical distress with automatic response. Continuous vitals monitoring with embedded safety logic.
04Research
Publications
IEEE · May 2023
Improving Data Integrity with Reversible Logic-based Error Detection and Correction Module on AHB-APB Bridge
Research on enhancing data integrity in bus bridge architectures using reversible logic, originating from the Maven Silicon internship project.
Grenze International Journal · Jun 2022
A Survey on Affordable Internet of Things (IoT) Enabled Healthcare Systems
Comprehensive survey on cost-effective IoT solutions for healthcare applications.
Patent
IN Patent No. 202341043496 · Issued Mar 28, 2025
A System for Controlling an Autonomous Vehicle and a Method Thereof
An intelligent safety system for autonomous vehicles that monitors driver vitals for medical distress and responds automatically to ensure occupant and road safety.
Granted05Skills
Domain
FA Tools
Languages
EDA / CAD
Other
Certifications
06Education
MSc Electrical Engineering
National University of Singapore
Specialization: Nanoelectronics
Graduate Assistant: EE2028 Microcontroller Programming & Interfacing · CG3207 Computer Architecture
BTech Electronics & Communication Engineering
SRM Institute of Science and Technology
07. what's next?
Let's connect.
Whether you're curious about failure analysis, want to talk semiconductor stuff, have a tool that needs building, or just want to connect, I am reachable. Open to collaborations and conversations about semiconductor engineering and failure analysis.