NAND EFA · Micron NTI · Singapore
Edidi Sai Anant.
I find out why bits misbehave.
Electrical Failure Analysis engineer at Micron's NAND Technology Integration group. I trace fail signatures back to root cause, build tools to make the process faster, and occasionally write code just because a script is more satisfying than a spreadsheet.
01About
Right now I'm at Micron Technology in Singapore, doing electrical failure analysis on NAND memory devices within the NTI (NAND Technology Integration) group. When a bit doesn't behave, I'm the one trying to figure out the electrical story behind it — verify the failure, localize the site, root-cause the physics.
Before that: an MSc in Electrical Engineering from NUS, where I got deep into memory technologies, VLSI design, and enough Cadence Virtuoso to have genuine opinions about it. I also TA'd microcontroller and computer architecture labs, which taught me a lot about explaining things clearly.
I'm a vibe coder at heart — I'd rather write a script than do the same thing twice, and I build tools and AI-assisted workflows for my team in Python. I find the intersection of hardware and software genuinely interesting, not just as a skill combination but as a way of thinking.
Outside of work: I solve puzzles, cook things that sometimes work, play video games, listen to music too loud, and travel when I can.
Currently
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NAND EFA Engineer Micron Technology · NTI · Singapore
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Tool builder Automation + AI for FA workflows
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Debug mindset Verify → Localize → Root-cause
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Vibe coding Python · whatever needs building
// Stored in long-term memory
02Work
NAND EFA Engineer @ Micron Technology
- Perform electrical failure analysis on NAND memory devices within the NTI (NAND Technology Integration) R&D group
- Investigate fail signatures to determine root cause — from electrical verification through physical localization and mechanism understanding
- Build Python-based automation tools and AI-assisted workflows to streamline FA triage and reporting
- Support yield and debug teams by translating electrical failure data into actionable engineering conclusions
- Work at the intersection of hardware characterization, circuit analysis, and software tooling
Graduate Assistant @ National University of Singapore
- TA for EE2028 (Microcontroller Programming and Interfacing) and CG3207 (Computer Architecture)
- Ran lab sessions, graded assignments, gave feedback on lab work
- Collaborated with faculty to overhaul lab materials — improved clarity and reduced common student errors
- Good reminder that explaining something clearly is its own skill
Project Intern @ Maven Silicon
- Designed a synthesizable AHB to APB bus bridge in Verilog HDL, including a reversible logic-based error detection and correction module
- Decomposed complex design into modular components from RTL through gate-level synthesis
- Turned this work into an IEEE publication — the paper came out of a genuine question about data integrity on bus architectures
Intern @ Sandeepani School of Embedded System Design
- Developed and verified a UART protocol implementation in Verilog HDL
- Ran functional verification of a Half Adder in SystemVerilog with QuestaSim coverage analysis
- First real exposure to verification methodology — random stimuli, coverage goals, the whole workflow
03Projects
VLSI Interconnect Modelling
Optimized processor interconnects using Elmore RC models and Cadence Virtuoso for a 2-core processor at 45nm technology. Focused on energy-delay tradeoffs and signal integrity.
Standard Cell IP Development
Ring oscillator Standard Cell IP in Cadence Virtuoso at 40nm. Hierarchical design, DRC/LVS clean, area-minimized with PVT corner analysis.
FPGA Hardware Accelerator
MLP neural network inference accelerator on Xilinx Zynq-7000. Implemented in software, HLS, and Verilog — profiled and optimized with pipelining, loop unrolling, and array partitioning.
In-Memory Compute Circuit
Designed an in-memory compute circuit using NeuroSim for neural network acceleration. Explored quantization (float64 → int4) and its effect on accuracy vs. efficiency tradeoffs.
AHB-APB Bridge + ECC
Synthesizable AHB to APB bridge with reversible logic-based error detection and correction module. Led to an IEEE publication on improving data integrity in bus bridge architectures.
Autonomous Vehicle Safety System
Intelligent system that detects driver medical distress and responds automatically. Continuous vitals monitoring with embedded safety response. Filed and granted a patent.
04Research
Publications
IEEE · May 2023
Improving Data Integrity with Reversible Logic-based Error Detection and Correction Module on AHB-APB Bridge
Research on enhancing data integrity in bus bridge architectures using reversible logic — grew out of the Maven Silicon internship project.
Grenze International Journal · Jun 2022
A Survey on Affordable Internet of Things (IoT) Enabled Healthcare Systems
Comprehensive survey on cost-effective IoT solutions for healthcare applications.
Patent
IN Patent No. 202341043496 · Issued Mar 28, 2025
A System for Controlling an Autonomous Vehicle and a Method Thereof
An intelligent safety system for autonomous vehicles that monitors driver vitals for medical distress and responds automatically to ensure occupant and road safety.
Granted05Skills
// what's actually stored in long-term memory